Short Path Timing

Q: What is short path timing effect?
A:
Short path effect is same as hold violation in clock skew.

Design techniques to minimize clock skew and minimize short path effect.

1. Add delay in data path:
Delays can be introduced in the data path to ensure that data arrives the destination FF in sync with the clock. Delays in data path can be introduced by adding buffers and/or inverters.

2. Clock reversing:
In this technique, clock is applied in reverse direction, clock reached the sink FF first and than to source FF. This ensures that the sink FF gates the input before the source changes its output.

3. Alternate Phase Clocking:
This is the most renowned method to avoid clock skew issues. There are two methods to implement this.

a. Clocking on alternate edge:
In this method, alternate registers are clocked on opposite edge of clock. This method gives a margin of one-half clock cycles.

b. Clock with two phases:
In this method, adjacent registers are alternately clocked on two different phases of same clock.