Clock Skew

Q: Define clock skew, negative clock skew and positive clock skew.

A:
Clock Skew:
In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.

Positive Clock Skew:
Positive skew occurs when the transmitting register receives the clock earlier than the receiving register.

Negative Clock Skew:
Negative skew occurs when the receiving register gets the clock earlier than the sending register.

Skew Violations:
Two kinds of violations can be caused by clock skew, hold violation, and setup violation.

1. Hold Violation:
The clock travels more slowly than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. Similar to short path problem.

2. Setup Violation:
If the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived.

A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Clock skew impact on clock period determination:
Clocks period must be greater than or equal to sum of transmitting registers "Clock to Q" delay, "Max path delay", receiving registers setup time, and difference between "clock skew to source register and clock skew to destination register".


References:
1. http://en.wikipedia.org/wiki/Clock_skew
2. http://www.actel.com/documents/Clock_Skew_AN.pdf